Priority is claimed to Japanese Application Number JP2006-179389 filed on Jun. 29, 2006, the disclosure of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor device in which a punch-through breakdown voltage between drain and source regions is improved, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
As an example of a conventional semiconductor device and a conventional method of manufacturing the semiconductor device, the following P-channel MOS transistor has been known. Firstly, a semiconductor substrate containing a P type impurity is prepared. Ions of phosphorus (P) are implanted and thermally diffused in a region where a P-channel MOS transistor is to be formed on the semiconductor substrate. Thereby, an N type well region is formed. Subsequently, ions of phosphorus (P) are implanted into the N type well region at an energy of 80 to 200 (KeV), and thereby an N type diffusion region is formed. By the annealing-heat treatment, the N type diffusion region is formed in a manner that an impurity concentration thereof is 1.0×1017 to 4.0×1017 (/cm3) in a region at a depth of about 0.4 to 0.7 (μm). Thereafter, P type diffusion regions as a source region and a drain region are formed in the N type well region, and a gate oxide film and a gate electrode are formed on the semiconductor substrate. The P-channel MOS transistor prevents a reduction in a punch-through breakdown voltage between the drain and source regions by forming the N type diffusion region. This technology is described, for instance, in Japanese Patent Application Laid-open Publication No. 2001-291781 (Pages. 9 to 11, and FIG. 1).
As described above, in the conventional semiconductor device, the N type diffusion region is formed in a deep portion of the N type well region in order to prevent the reduction in the punch-through breakdown voltage between the drain and source regions. In a channel region formed in the N type well region, a fluctuation in the impurity concentration is likely to occur due to the influence at the time of forming the N type diffusion region, and thereby there is a problem in this structure that an appropriate threshold voltage (Vth) of the MOS transistor changes. Furthermore, there is another problem that it is difficult to reduce the threshold voltage and on-resistance of is another problem that it is difficult to reduce the threshold voltage and on-resistance of the MOS transistor in a case where the impurity concentration of the channel region is increased due to the fluctuation in the impurity concentration in the channel region of the MOS transistor.
Moreover, in the conventional method of manufacturing a semiconductor device, after the N type well region is formed in the region where the P-channel MOS transistor is formed on the semiconductor substrate, the N type diffusion region is formed. Then, there is a case where the N type diffusion region is formed apart from a desired region with respect to the source and drain regions due to mask misalignment at the time of forming the N type diffusion region, or at the time of forming the source and drain regions. In this manufacturing method, there is a problem that the punch-through breakdown voltage between the drain and source regions is reduced, and thereby the breakdown voltage characteristic of the MOS transistor is deteriorated.
Furthermore, in the conventional method of manufacturing a semiconductor device, after the N type well region is formed in the region where the P-channel MOS transistor is formed on the semiconductor substrate, the N type diffusion region is formed. There is a problem in this manufacturing method that it is difficult to reduce the size of the MOS transistor, since it is necessary to take account of degrees of mask misalignment at the time of forming the N type diffusion region, the source and drain regions.
In addition, in the conventional method of manufacturing a semiconductor device, after the N type well region is formed in the region where the P-channel MOS transistor is formed on the semiconductor substrate, the N type diffusion region is formed. There is a problem in this manufacturing method that the number of manufacturing steps and the number of masks increase, and thereby it is difficult to reduce the manufacturing cost.